1. Field of the Invention
This invention relates to a semiconductor device in which a plurality of photodiodes are formed in the substrate.
1. Description of the Prior Art
FIG. 4 shows such a semiconductor device of the prior art. In this device, an n-type epitaxial growth layer 2 is formed on a p-type substrate 1, thereby forming a semiconductor substrate structure 10. An n.sup.+ -type buried region 3 is formed in the middle of the boundary between substrate 1 and epitaxial growth layer 2. A p-type anode region 5 is formed on the surface of epitaxial growth layer 2, by ion implanting or diffusion process, and n.sup.+ -type cathode regions 6 formed on the same surface, surrounding the anode region and being spaced therefrom at a predetermined distance. A photodiode is now formed, comprising p-type anode and n-type cathode regions. Furthermore, as shown in FIG. 5(a), an anode electrode 15 is provided in anode region 5, cathode electrodes 16 in cathode regions 6, and a substrate electrode 11 on the bottom surface of substrate 1, being connected to ground potential, to complete the photodiode. A plurality of p.sup.+ -type isolation regions 4 are formed in epitaxial growth layer 2 to isolate each photodiode from one another.
When light rays are incident on the photodiode as shown in FIG. 5(a), electron-hole pairs are generated in the vicinity of the p-n junction of the photodiode. If a zero or reverse bias voltage is applied across the p-n junction, the holes of the generated electron-hole pairs will drift, across the depletion region formed close to anode region 5, so that a photocurrent flows across the photodiode, thus transforming an optical input to an electrical signal.
In the semiconductor photodiode device of the structure of FIG. 4, a photodiode D.sub.1 is formed by anode and cathode regions 5 and 6 close to isolation regions 4 and since isolation region 4 is p.sup.+ type, a parasitic photodiode D.sub.2 is formed, as indicated by a dashed line, as shown in FIG. 5(a) FIG. 5(b) shows an equivalent circuit schematic comprising the photodiode and the parasitic diode. Designating I.sub.1 being the current flowing into the device, I.sub.PD1, the photocurrent of photodiode D.sub.1, and I.sub.PD2 the photocurrent of parasitic photodiode D.sub.2, it can be obtained that: EQU I.sub.1 =165.7 (.mu.A) EQU I.sub.PD1 =93.9 (.mu.A) and EQU I.sub.PD2 =70.6 (.mu.A)
Then, it may be established that: EQU I.sub.1 .apprxeq.I.sub.PD1 +I.sub.PD2
For photodiode D.sub.1, photodiode D.sub.2 is nothing less than a parasitic diode. Photocurrent I.sub.PD2 of parasitic photodiode D.sub.2 depends on several factors including the wave length of irradiated light rays, the lot to lot variance in quality in the manufactured semiconductor substrate, and the bias voltage applied to the device. Photocurrent I.sub.PD1 in the n-type side of photodiode D.sub.1 inherently includes the effect of the parasitic element. This effect of the parasitic element degrades the design accuracy of the device. For example, the presence of parasitic photodiode D.sub.2 facilitates the holes generated in the lower portion of cathode regions 6 to drift toward isolation region 4, the extent of which increases as the reverse bias voltage increases, thus reducing the p-type side of photo current I.sub.PD1 of photodiode D.sub.1.
When photodiode D.sub.1 is forward-biased, a p-n-p type parasitic transistor is formed with the emitter of the parasitic transistor disposed in anode region 5 of diode D.sub.1, the base in cathode regions 6, and the collector in isolation regions 4. Then, the current flows from anode region 5 to isolation regions 4 and substrate 1, thus causing the substrate potential to rise. This rise of the substrate potential adversely affects the performance of the external circuit (not shown), connected to the device via isolation regions 4 in the photodiode.
The problem becomes more severe as photodiode D.sub.1 is disposed closer to isolation regions 4 to increase the circuit packaging density. A simple measure to solve the problem is to separate photodiode 5 from isolation regions 4 at a sufficient distance. However, this measure increases the occupying area for the element in the device, adversely affecting the circuit packaging density, particularly important when the circuit is fabricated into an integrated circuit device. Furthermore, this measure does not completely eliminate the problem associated with the parasitic element.